Method for forming pattern

ABSTRACT

A method for forming a pattern according to an embodiment, includes forming a first film pattern having a wide width dimension above a processed film; forming a second film pattern covering a portion of the first film pattern and a third film pattern connected to the second film pattern together above the processed film, the third film pattern having a width dimension narrower than the first film pattern, and to be a line pattern of a line and space pattern; forming a fourth film pattern on a side face of the first film pattern and a plurality of film patterns by the fourth film to be a line pattern of a line and space pattern on both side faces of the third film pattern; and removing the second film pattern and the third film pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromU.S. Patent Application No. 61/694,602 filed on Aug. 29, 2012 in U.S.A.,the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a method for forming apattern.

BACKGROUND

In fine patterning of semiconductor devices, fine patterning relying ononly optical lithography technology whose limit is being reached ismoving to a new stage thanks to double patterning technology based onconventional optical lithography technology. Various kinds of doublepatterning technology have been developed/published and the currentlymainstream technology includes a sidewall process.

The sidewall process is a process in which a line & space (L/S) patternwith a double pitch is formed by optical lithography technology and thepattern is slimmed and used as a core material to form a sidewall filmon the sidewall thereof. Then, the core material is removed and adesired pitch pattern is formed by etching a desired processed filmusing the remaining sidewall film or a foundation film processed basedon the sidewall film as a hard mask. Though the above sidewall processhas a long process flow and is complicated when compared with a normalsingle exposure process, a pattern by lithography only needs to beformed with double the desired pitch and added processes for slimmingand sidewall formation are diverted from conventional technology andtherefore, finer patterning can advantageously be developed easily whilecurbing investment.

A major feature of pattern formation by the sidewall process is that theline width is controlled by controlling the thickness of a sidewallfilm. In a process of forming a pattern of only a simple line & pattern,the pattern can be formed by controlling the width of a core materialand the thickness of a sidewall film. However, wiring layers in upperand lower layers are connected to a wiring pattern in an actualsemiconductor device via a hole pattern to configure a semiconductorcircuit and thus, it is necessary to arrange a wide wiring pattern inplaces in a pattern layout. Because, as described above, the wire widththat can be formed by the sidewall process is determined by thethickness of a sidewall film, such a wide pattern is normally addedseparately after undergoing the sidewall process.

However, problems that are not considered when various patternvariations are formed by conventional optical lithography are caused byadding the wide pattern. For example, a case when a wide pattern isexposed and developed after being aligned with a sidewall pattern usingoptical lithography and then, a lower-layer film is etched by using afilm pattern configured by the wide pattern and the sidewall pattern asa mask can be considered. However, according to such a technique, it isnecessary to expose a sidewall pattern portion by developing the widepattern. For a positive resist, for example, the resist buried in thesidewall pattern portion needs to be removed by sensitizing fordevelopment. However, the sidewall pattern is formed in fine dimensionsless than the resolution limit of exposure and thus, exposure light doesnot reach a resist near the lower portion of the sidewall pattern andthe resist cannot be removed by development and thus, a resist residuearises. As a result, the resist residue is transferred also in thesubsequent transfer of the sidewall pattern to a lower-layer film,posing a problem of a short of the sidewall pattern.

If a negative resist is used instead of a positive resist, there is noneed to shine light on the sidewall pattern portion and the sidewallpattern portion can be exposed only by adjusting the developing time,but in this case, a problem of a collapsing sidewall pattern due tosurface tension of water is caused in a rinsing/drying process after thedevelopment.

It is possible here to consider coexistence of a sidewall pattern and awide pattern by forming a coating-type organic film on a wafer after thesidewall pattern being formed for planarization of steps by the sidewallpattern and then performing an optical lithography process of the widepattern and etching the coating-type organic film using a resist as amask. According to such a technique, however, a problem like thecollapse of sidewall patterns by random air gaps generated by poorembedding between sidewall patterns when the coating-type organic filmis coated arises. Also, a problem of difficulty of ensuring the neededthickness (height) of the sidewall pattern to process a lower-layer filmwhen the coating-type organic film is etched arises.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart showing principal part processes of a method forfabricating a semiconductor device according to a first embodiment;

FIGS. 2A to 2C are a process top view and process sectional views of themethod for fabricating a semiconductor device according to the firstembodiment;

FIGS. 3A to 3C are a process top view and process sectional views of themethod for fabricating a semiconductor device according to the firstembodiment;

FIGS. 4A to 4C are a process top view and process sectional views of themethod for fabricating a semiconductor device according to the firstembodiment;

FIGS. 5A to 5C are a process top view and process sectional views of themethod for fabricating a semiconductor device according to the firstembodiment;

FIGS. 6A to 6C are a process top view and process sectional views of themethod for fabricating a semiconductor device according to the firstembodiment;

FIGS. 7A and 7B are process sectional views of the method forfabricating a semiconductor device according to the first embodiment;

FIGS. 8A to 8C are a process top view and process sectional views of themethod for fabricating a semiconductor device according to the firstembodiment;

FIGS. 9A to 9C are a process top view and process sectional views of themethod for fabricating a semiconductor device according to the firstembodiment;

FIGS. 10A to 10C are a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment;

FIGS. 11A to 11C are a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment;

FIG. 12 is a top view exemplifying a wire formed by the method forfabricating a semiconductor device according to the first embodiment;

FIGS. 13A to 13C are conceptual diagrams illustrating conditions of ahook-up according to a comparative example of the first embodiment;

FIGS. 14A and 14B are conceptual diagrams illustrating conditions of thehook-up according to the first embodiment; and

FIG. 15 is a conceptual diagram illustrating a resist residue of asidewall pattern according to the comparative example of the firstembodiment.

DETAILED DESCRIPTION First Embodiment

A method for forming a pattern according to an embodiment, includesforming a processed film above a substrate; forming a first film patternhaving a wide width dimension above the processed film; forming a secondfilm pattern covering a portion of the first film pattern and a thirdfilm pattern connected to the second film pattern together above theprocessed film, the third film pattern having a width dimension narrowerthan the first film pattern, and to be a line pattern of a line andspace pattern; forming a fourth film conformally so as to cover aremaining portion of the first film pattern, the second film pattern,and the third film pattern; forming a film pattern by the fourth film ona side face of the first film pattern and a plurality of film patternsby the fourth film to be a line pattern of a line and space pattern onboth side faces of the third film pattern, by etching the fourth filmuntil a remaining portion surface of the first film pattern, a surfaceof the second film pattern, and a surface of the third film pattern areexposed; removing the second film pattern and the third film pattern;and etching the processed film by using the plurality of film patternsby the fourth film formed on the both side faces of the third filmpattern and a wide pattern formed by combining the first film patternand the film pattern by the fourth film formed on the side face of thefirst film pattern as masks.

The first embodiment will be described below using the drawings.

FIG. 1 is a flowchart showing principal part processes of a method forfabricating a semiconductor device according to a first embodiment. InFIG. 1, the method for fabricating a semiconductor device according tothe first embodiment executes a series of processes including aconductive material film formation process (S102), a silicon nitride(SiN) film formation process (S104), a wide pattern formation process(S106), an organic film coating process (S108), a Spin on Glass (SOG)film formation process (S110), a resist pattern formation process(S112), an etching process (S114), a slimming process (S116), a sidewallmaterial film formation process (S118), an etch-back process (S120), acore material removal process (S122), a SiN film etching process (S124),and a conductive material film etching process (S126).

FIGS. 2A to 2C show a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment. FIGS. 2A to 2C show the conductive material film formationprocess (S102) to the wide pattern formation process (S106). Subsequentprocesses will be described later.

FIG. 2A shows a top view. FIG. 2B shows a process sectional view of ahook-up region (first region) of a chip formed on a substratecorresponding to an A-A′ section in FIG. 2A. FIG. 2C shows a processsectional view of a wiring region (second region) of the chip formed onthe substrate corresponding to a B-B′ section in FIG. 2A.

First, as the conductive material film formation process (S102), aconductive material film 210 is formed on a semiconductor substrate (anexample of the substrate) by using the chemical vapor deposition (CVD)method to a thickness of, for example, 50 nm. A polysilicon film issuitably used as a material of the conductive material film 210(conductive film). In addition to polysilicon, a conductive materialthat can be etched is suitably used as a material of the conductivematerial film 210. For example, a silicon wafer of 300 mm in diameter isused as the semiconductor substrate 200. A gate dielectric film,interpoly dielectric film or the like to form a device portion may beformed on the semiconductor substrate 200. Alternatively, a layer havingvarious semiconductor elements or structures (not shown) such as adevice portion, contact plug layer, and other metal wires may be formed.Alternatively, other layers may be formed.

Then, as the SiN film formation process (S104), a silicon nitride (SiN)film 212 is formed on the conductive material film 210 by using the CVDmethod or the like to a thickness of, for example, 50 nm. The SiN film212 is used as a hard mask material when the conductive material film210 is etched. In the method for forming a pattern in the firstembodiment, the SiN film 212 becomes an example of a processed film toform a pattern of a hard mask.

Next, as the wide pattern formation process (S106), a plurality of filmpatterns 220, 222 (first film patterns or first convex patterns) isformed on the SiN film 212 in a line width and pitch wider than apattern to form a wire in the wiring region. Here, for example, anamorphous silicon (a-Si) film is first formed on the SiN film 212 byusing the CVD method or the like. Then, as shown in FIGS. 2A and 2B, thefilm patterns 220, 222 (wide patterns) of an a-Si film are formed in thehook-up region in a line width and pitch sufficiently wider than a line& space pattern formed in the wiring region. In this stage, as shown inFIG. 2C, no pattern to form a wire is formed in the wiring region. Inthe first embodiment, a film pattern (first film pattern) wider than thewire width is formed before a pattern to form a wire in the wiringregion is formed by the sidewall process.

FIGS. 3A to 3C show a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment. FIGS. 3A to 3C show the organic film coating process (S108)in FIG. 1. Subsequent processes will be described later.

FIG. 3A shows a top view. FIG. 3B shows a process sectional view of thehook-up region of the chip formed on the substrate corresponding to anA-A′ section in FIG. 3A. FIG. 3C shows a process sectional view of thewiring region of the chip formed on the substrate corresponding to aB-B′ section in FIG. 3A.

In FIGS. 3A to 3C, as the organic film coating process (S108), after thefirst film patterns being formed, the whole substrate 200 is coated withan organic film 230 (coated organic film) to form the organic film 230like covering the film patterns 220, 222 of the a-Si film. The surfaceof the substrate 200 is planarized by coating of the organic film 230.After the coating, a crosslinking reaction may be caused by, forexample, baking at 300° C.

FIGS. 4A to 4C show a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment. FIGS. 4A to 4C show the SOG film formation process (S110)and the resist pattern formation process (S112) in FIG. 1. Subsequentprocesses will be described later.

FIG. 4A shows a top view. FIG. 4B shows a process sectional view of thehook-up region of the chip formed on the substrate corresponding to anA-A′ section in FIG. 4A. FIG. 4C shows a process sectional view of thewiring region of the chip formed on the substrate corresponding to aB-B′ section in FIG. 4A.

In FIGS. 4A to 4C, as the SOG film formation process (S110), a Spin onGlass (SOG) film 232 is first formed on the organic film 230 by usingthe coating process to a thickness of, for example, 30 nm.

Next, as the resist pattern formation process (S112), the whole surfaceof the substrate 200 is first coated with a resist. Then, a wide patternis exposed in the hook-up region so as to extend over the two filmpatterns 220, 222 of the a-Si film by using lithography technology. Inthe wiring region, a 1:1 line & space pattern is exposed. Then, a resistpattern 240 extending over the two film patterns 220, 222 of the a-Sifilm is formed in the hook-up region and a resist pattern 242 to be a1:1 line & space pattern is formed in the wiring region. At this point,as shown in FIGS. 4A and 4B, the resist pattern 240 is formed so as notto cover the side face of the film pattern 220 of the a-Si film on theside opposite to the arrangement direction of the film pattern 222 ofthe a-Si film. Similarly, the resist pattern 240 is formed so as not tocover the side face of the film pattern 222 of the a-Si film on the sideopposite to the arrangement direction of the film pattern 220 of thea-Si film. The resist pattern 240 is formed so as to overlap with eachof the film patterns 220, 222 of the a-Si film in an overlapping widthlarger than half the line width of the resist pattern 242. The resistpattern 242 shown in FIGS. 4A and 4C is suitably formed in a line widthso that half the line width is less than the resolution limit ofexposure. Moreover, as shown in FIG. 4A, the resist pattern 242 isformed so that at least one of convex line patterns constituting theresist pattern 242 formed in the wiring region is connected to theresist pattern 240 formed in the hook-up region. In the example in FIG.4A, a center line pattern is connected to the resist pattern 240. Convexline patterns constituting the resist pattern 242 other than the centerline pattern are each connected to corresponding wide resist patterns(not shown) by, for example, changing orientation 90 degrees before theresist pattern 240. Because the substrate surface has been planarized bythe organic film coating process (S108), the resist patterns 240, 242can be formed with high precision.

FIGS. 5A to 5C show a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment. FIGS. 5A to 5C show the etching process (S114) in FIG. 1.Subsequent processes will be described later.

FIG. 5A shows a top view. FIG. 5B shows a process sectional view of thehook-up region of the chip formed on the substrate corresponding to anA-A′ section in FIG. 5A. FIG. 5C shows a process sectional view of thewiring region of the chip formed on the substrate corresponding to aB-B′ section in FIG. 5A.

In FIGS. 5A to 5C, as the etching process (S114), the SOG film 232 isfirst etched by using the resist patterns 240, 242 as masks. Next, theorganic film 230 is etched by using the etched SOG film 232 as a mask. Afilm pattern 234 of the organic film 230 covering portions of the filmpatterns 220, 222 of the a-Si film is formed, as shown in FIG. 5B, onthe SiN film 212 (processed film) by the etching. Also, as shown inFIGS. 5A and 5C, a film pattern 236 of the organic film 230 connected tothe film pattern 234 of the organic film 230, having a narrower widthdimension than the film pattern 220, 222 of the a-Si film, and becominga line pattern of a line & space pattern is formed on the SiN film 212(processed film). A plurality of the film patterns 236 of the organicfilm 230 arranged side by side is each connected to the correspondingwide film patterns of the organic film (not shown) by changingorientation to the outer side before the film pattern 234 of the organicfilm 230 in the center. Thus, sets each including the film pattern 234of the organic film 230 extending over a pair of the film patterns 220,222 of the a-Si film and the film pattern 236 of the organic film 230connected to the film pattern 234 of the organic film 230 and to be aline pattern are formed. By forming such sets, two sets of combinationof a wide pattern of the hook-up and a line pattern to be a wire can beformed by the sidewall processing process described later from each set.The film pattern 234 of the organic film 230 is formed so as to overlapwith each of the film patterns 220, 222 of the a-Si film in anoverlapping width larger than half the line width of the film pattern236 as a line pattern.

FIGS. 6A to 6C show a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment. FIGS. 6A to 6C show the slimming process (S116) in FIG. 1.Subsequent processes will be described later.

FIG. 6A shows a top view. FIG. 6B shows a process sectional view of thehook-up region of the chip formed on the substrate corresponding to anA-A′ section in FIG. 6A. FIG. 6C shows a process sectional view of thewiring region of the chip formed on the substrate corresponding to aB-B′ section in FIG. 6A.

In FIGS. 6A to 6C, as the slimming process (S116), slimming processingof the film pattern 234 of the organic film 230 and the plurality offilm patterns 236 of the organic film 230 is performed. Slimmingprocessing is performed so that, for example, the line width dimensionof the plurality of film patterns 236 of the organic film 230 to be aline pattern of a line & space pattern is halved. At this point, theline width of the film pattern 234 of the organic film 230 is alsoslimmed by a width corresponding to half the line width dimension of thefilm pattern 236. By the slimming processing, as shown in FIGS. 6A and6C, a plurality of film patterns 237 (third film pattern) of the organicfilm 230 to be a 1:3 line & space pattern can be formed in the wiringregion. Also by the slimming processing, as shown in FIGS. 6A and 6B, afilm pattern 235 (second film pattern) extending over the film patterns220, 222 of the a-Si film can be formed in the hook-up region. The filmpattern 234 of the organic film 230 before the slimming processing isformed so as to overlap with each of the film patterns 220, 222 of thea-Si film in an overlapping width larger than half the line width of theplurality of film patterns 236 and thus, the two film patterns 220, 222of the a-Si film to be a pair can be prevented from opening a gaptherebetween also after the slimming processing. In other words, thefilm 235 can be formed between the two film patterns 220, 222 of thea-Si film to be a pair so that the SiN film 212 is not exposed.

FIGS. 7A and 7B show process sectional views of the method forfabricating a semiconductor device according to the first embodiment.FIGS. 7A and 7B show the sidewall material film formation process (S118)in FIG. 1. Subsequent processes will be described later.

FIG. 7A shows a process sectional view of a hook-up region of the chipformed on the substrate. FIG. 7B shows a process sectional view of awiring region of the chip formed on the substrate.

In FIGS. 7A and 7B, as the sidewall material film formation process(S118), a sidewall material film 250 (fourth film) is conformally formedon the substrate so as to cover remaining portions of the film patterns220, 222 of the a-Si film that are not covered with the film pattern 235of the organic film 230, the film pattern 235 of the organic film 230,and the plurality of film patterns 237 of the organic film 230 after theslimming processing. A silicon oxide film (SiO₂ film) is suitably usedas the sidewall material film 250. The plasma CVD method can suitably beused as the formation method because the sidewall material film 250 canbe formed at ordinary temperature or low temperature near the ordinarytemperature and the organic film 230 can be prevented from melting.

FIGS. 8A to 8C show a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment. FIGS. 8A to 8C show the etch-back process (S120) in FIG. 1.Subsequent processes will be described later.

FIG. 8A shows a top view. FIG. 8B shows a process sectional view of thehook-up region of the chip formed on the substrate corresponding to anA-A′ section in FIG. 8A. FIG. 8C shows a process sectional view of thewiring region of the chip formed on the substrate corresponding to aB-B′ section in FIG. 8A.

In FIG. 8A to 8C, as the etch-back process (S120), the sidewall materialfilm 250 is etched until the surface of remaining portions of the filmpatterns 220, 222 of the a-Si film that are not covered with the filmpattern 235 of the organic film 230, the surface of the film pattern 235of the organic film 230, and the surface of the plurality of filmpatterns 237 of the organic film 230 are exposed. Accordingly, as shownin FIGS. 8A and 8B, a film pattern 254 by the sidewall material film 250(film pattern of the fourth film) is formed on the side face (outer sideface) that is not covered with the film pattern 235 of the organic film230 of both side faces of the film pattern 220 of the a-Si film. At thesame time, a film pattern 252 by the sidewall material film 250 (filmpattern of the fourth film) is formed on the side face (outer side face)that is not covered with the film pattern 235 of the organic film 230 ofboth side faces of the film pattern 222 of the a-Si film. At the sametime, film patterns 251, 253 by the sidewall material film 250 areformed on both sidewalls of the film pattern 235 of the organic film230. Further, as shown in FIGS. 8A and 8C, a plurality of film patterns256 by the sidewall material film 250 (film pattern of the fourth film)in a line width less than the resolution limit of exposure is formed onboth side faces of the plurality of film patterns 237 of the organicfilm 230. The film pattern 256 by the sidewall material film 250 isformed on both side faces of each of the plurality of film patterns 237of the organic film 230. The film pattern 235 of the organic film 230and the film patterns 237 of the organic film 230 connected theretohave, as shown in FIG. 8A, film patterns 251, 253, 256 by the sidewallmaterial film 250 formed so as to surround the side faces of the filmpattern 235 and the film pattern 237.

FIGS. 9A to 9C show a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment. FIGS. 9A to 9C show the core material removal process (S122)in FIG. 1. Subsequent processes will be described later.

FIG. 9A shows a top view. FIG. 9B shows a process sectional view of thehook-up region of the chip formed on the substrate corresponding to anA-A′ section in FIG. 9A. FIG. 9C shows a process sectional view of thewiring region of the chip formed on the substrate corresponding to aB-B′ section in FIG. 9A.

In FIGS. 9A to 9C, as the core material removal process (S122), the filmpattern 235 of the organic film 230 and the plurality of film patterns237 of the organic film 230 to be a core material are removed by the dryashing method. Accordingly, as shown in FIGS. 9A and 9B, the filmpattern 220 of the a-Si film and the film pattern 254 by the sidewallmaterial film 250 in contact with one sidewall (outer sidewall) of thefilm pattern 220 of the a-Si film can be left. At the same time, thefilm pattern 222 of the a-Si film and the film pattern 252 by thesidewall material film 250 in contact with one sidewall (outer sidewall)of the film pattern 222 of the a-Si film can be left. According to theabove technique, a wide pattern (first wide pattern) wider than the filmpattern 220 of the a-Si film in width can be formed by combining thefilm pattern 220 of the a-Si film and the film pattern 254 by thesidewall material film 250. Similarly, a wide pattern (second widepattern) wider than the film pattern 222 of the a-Si film in width canbe formed by combining the film pattern 222 of the a-Si film and thefilm pattern 252 by the sidewall material film 250. In the wiringregion, on the other hand, as shown in FIGS. 9A and 9C, the plurality offilm patterns 256 by the sidewall material film 250 to be a line patternof a 1:1 line & space pattern that secures a sufficient thickness(height) to process a lower-layer film can be formed.

From the above, according to the first embodiment, the two film patterns220, 222 (first convex patterns) of the a-Si film having a wide widthdimension and to be a pair can be formed side by side in a position ofthe hook-up (hook-up region) on the substrate. Then, the film patterns252, 254 (second convex patterns) by the sidewall material film 250 canbe formed on the outer side face of the two film patterns 220, 222 ofthe a-Si film respectively. Accordingly, a wide pattern (first widepattern) by combining the film pattern 220 of the a-Si film and the filmpattern 254 by the sidewall material film 250 formed on the sidewall ofthe film pattern 220 can be formed in the hook-up region. Similarly, awide pattern (second wide pattern) by combining the film pattern 222 ofthe a-Si film and the film pattern 252 by the sidewall material film 250formed on the sidewall of the film pattern 222 can be formed. At thesame time, the film pattern 256 (third convex pattern) by the sidewallmaterial film 250 connected to the wide pattern by combining the filmpattern 220 of the a-Si film and the film pattern 254 by the sidewallmaterial film 250 and to be a line pattern of a line & space pattern canbe formed in the wiring position (wiring region) on the substrate.Similarly, the film pattern 256 (third convex pattern) by the sidewallmaterial film 250 connected to the wide pattern by combining the filmpattern 222 of the a-Si film and the film pattern 252 by the sidewallmaterial film 250 and to be a line pattern of a line & space pattern canbe formed. Thus, the corresponding one of two adjacent line patterns ofline & space patterns is connected to each of the two wide patterns tobe a pair.

As shown in FIG. 9A, the two film patterns 252, 254 by the sidewallmaterial film 250 and the two film patterns 256 by the sidewall materialfilm 250 to be two adjacent line patterns of line & space patterns, eachof which connected to the corresponding one of the film patterns 252,254, can be formed in substantially the same line width less than theresolution limit of exposure.

According to the first embodiment, as described above, the film pattern235 of the organic film 230 is formed between the two aligned filmpatterns 220, 222 of the a-Si film to be a pair so as to extend over thetwo aligned film patterns 220, 222 of the a-Si film. Then, the filmpattern 237 of the organic film 230 to be one line pattern of line &space pattern connected to the film pattern 235 of the organic film 230is formed. Then, by performing the sidewall processing using the organicfilm 230 as a core material, a pair of adjacent wide patterns and a pairof adjacent line patterns of line & space patterns, each of whichconnected to the corresponding wide pattern, can be formed. Thus,according to the first embodiment, a set of connected wide patterns isformed for each pair of adjacent line patterns.

FIGS. 10A to 10C show a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment. FIGS. 10A to 10C show the SiN film etching process (S124).Subsequent processes will be described later.

FIG. 10A shows a top view. FIG. 10B shows a process sectional view ofthe hook-up region of the chip formed on the substrate corresponding toan A-A′ section in FIG. 10A. FIG. 10C shows a process sectional view ofthe wiring region of the chip formed on the substrate corresponding to aB-B′ section in FIG. 10A.

In FIGS. 10A to 10C, as the SiN film etching process (S124), the SiNfilm 212 is etched by using the plurality of film patterns 256 (thirdconvex patterns) by the sidewall material film 250 formed by etching thesidewall material film 250 and to be a line pattern, a wide patterncombining the film pattern 254 (second convex pattern) by the sidewallmaterial film 250 and the film pattern 220 of the a-Si film, and a widepattern combining the film pattern 252 (second convex pattern) by thesidewall material film 250 and the film pattern 222 of the a-Si film asmasks. Accordingly, as shown in FIGS. 10A and 10B, a wide pair of filmpatterns 214 by the SiN film 212 having substantially the same widthdimension as a pair of wide patterns combining the film patterns 220,222 of the a-Si film and the film patterns 254, 256 by the sidewallmaterial film 250 can be formed in the hook-up region. At the same time,as shown in FIGS. 10A and 10C, a plurality of film patterns 216 by theSiN film 212 to be a line pattern of a 1:1 line & space pattern can beformed in the wiring region.

According to the first embodiment, as described above, a 1:1 line &space pattern in dimensions less than the resolution limit of exposurecan be formed at the same time while forming a pair of wide patterns.

FIGS. 11A to 11C show a process top view and process sectional views ofthe method for fabricating a semiconductor device according to the firstembodiment. FIGS. 11A to 11C show the conductive material film etchingprocess (S126) in FIG. 1.

FIG. 11A shows a top view. FIG. 11B shows a process sectional view ofthe hook-up region of the chip formed on the substrate corresponding toan A-A′ section in FIG. 11A. FIG. 11C shows a process sectional view ofthe wiring region of the chip formed on the substrate corresponding to aB-B′ section in FIG. 11A.

In FIGS. 11A to 11C, as the conductive material film etching process(S126), after the SiN film 212 being etched, the conductive materialfilm 210 is etched by using the film pattern 214 of the remaining SiNfilm 212 as a mask. Accordingly, a pair of wide patterns are transferredto the conductive material film 210 in the hook-up region so that, asshown in FIGS. 11A and 11B, the film pattern 211 of the wide conductivematerial film 210 can be formed. At the same time, a sidewall pattern bysidewall processing is transferred to the conductive material film 210in the wiring region so that, as shown in FIGS. 11A and 11C, a pluralityof film patterns 213 by the conductive material film 210 to be a linepattern of a 1:1 line & space pattern can be formed.

FIG. 12 is a top view exemplifying a wire formed by the method forfabricating a semiconductor device according to the first embodiment. Asshown in FIG. 12, the plurality of film patterns 213 by the conductivematerial film 210 to be a line pattern of a 1:1 line & space pattern canbe formed as wires by cutting off ends of the plurality of film patterns213 by the conductive material film 210 that are connected adjacent toeach other in the end. The one film pattern 213 can be connected to eachof the two film patterns 211 to be paired of the wide conductivematerial film 210. Then, the film pattern 211 of the wide conductivematerial film 210 remaining after etching using as the next mask theremaining SiN film 212 remaining after etching using film patterns ofthe film patterns 252, 254 by the sidewall material film 250 formed onthe side face of the film patterns 220, 222 of the a-Si film and thefilm patterns 220, 222 of the a-Si film as masks is used as a hook-up.

FIGS. 13A to 13C are conceptual diagrams illustrating conditions of ahook-up according to a comparative example of the first embodiment. FIG.13A shows a case when a wide pattern of a hook-up 10 is formed as anL1:S1 (L1>S1) line & space pattern in an inter-level dielectric 30 on asubstrate 12. Then, a contact 20 is connected to the hook-up 10. FIG.13A also shows a case when the four hook-ups 10 are formed in adimension A1. In the dimension configuration shown in FIG. 13A, thewidth S1 to be a space pattern becomes narrow and a problem of shortwhen a pattern is formed by lithography could occur. If the wide patternof the hook-up 10 is formed, as shown in FIG. 13B, as an L1:S2 (S2>S1)line & space pattern to avoid such a problem, this time a problem of anincreased chip size from A1 to A2 occurs for an increase of the spacepattern size. Conversely, if the wide pattern of the hook-up 10 isformed, as shown in FIG. 13C, as an L2:S2 (L2=S2) line & space patternto maintain the chip size at A1, a problem of the shifted contact 20could occur.

FIGS. 14A and 14B are conceptual diagrams illustrating conditions of thehook-up according to the first embodiment. FIG. 14A shows a case when,like FIG. 13A showing the above comparative example, a wide pattern ofthe hook-up 10 is formed as an L1:S1 (L1>S1) line & space pattern in theinter-level dielectric 30 on the substrate 12. Then, the contact 20 isconnected to the hook-up 10. FIG. 14A also shows a case when the fourhook-ups 10 are formed in the dimension A1. According to the firstembodiment, by contrast, a sidewall pattern 14 can be added to one sideface of the hook-up 10 and thus, even if the wide pattern of the hook-up10 is formed, as shown in FIG. 14B, as the L2:S2 (L2=S2) line & spacepattern to maintain the chip size at A1, a wide pattern 16 combining thehook-up 10 and the sidewall pattern 14 can be formed. Therefore, theshifted contact 20 can be avoided while maintaining the chip size at A1.

FIG. 15 is a conceptual diagram illustrating a resist residue of asidewall pattern according to the comparative example of the firstembodiment. The comparative example shows a case when, after a sidewallpattern 50 being formed in a width less than the resolution limit, thesidewall pattern 50 is coated with a resist to form, for example, a widepattern in a region outside the wiring region by lithography technology.In such a case, as described above, exposure light does not reach aresist near a lower portion of the sidewall pattern 50 and the resistcannot be removed by development and thus, a resist residue 52 arises.However, according to the first embodiment, a wide pattern is alreadyformed before a sidewall pattern in a width less than the resolutionlimit is formed and thus, such a problem as a resist residue betweensidewall patterns does not arise. Also according to the firstembodiment, a conventional problem of the collapse of sidewall patternsdue to surface tension of water in a rinsing/drying process after thedevelopment can be avoided. Moreover, the occurrence of random air gapsgenerated by poor embedding generated by coating of a coating organicfilm between sidewall patterns after the sidewall patterns being formedcan be avoided. Further, as described above, the thickness (height) ofthe sidewall pattern to process a lower-layer film can be secured.

In the foregoing, embodiments have been described with reference toconcrete examples. However, the present disclosure is not limited to theconcrete examples. According to the flow chart shown in FIG. 1, forexample, the slimming process (S116) is performed after the etchingprocess (S114), but slimming processing on the resist pattern 240, 242shown in FIGS. 4A to 4C after the resist pattern formation process(S112) may be performed or slimming processing on the SOG film 232 towhich the resist patterns 240, 242 have been transferred may beperformed in the etching process (S114). Alternatively, slimmingprocessing on the film patterns 234, 236 of the organic film 230 shownin FIGS. 6A to 6C and slimming processing on the resist patterns 240,242 or the SOG film 232 may be combined.

In addition, all methods for forming a pattern, all semiconductordevices, and all methods for fabricating a semiconductor device thatinclude elements of the present embodiment and whose design can bechanged as appropriate by persons skilled in the art are included in thescope of the present disclosure.

While techniques normally used in the semiconductor industry such ascleaning before and after treatment are not described for convenience ofdescription, it is needless to say that such techniques are included inthe scope of the present disclosure.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel methods and devices describedherein may be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the methods anddevices described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

What is claimed is:
 1. A method for forming a pattern, comprising:forming a processed film above a substrate; forming a first film patternhaving a wide width dimension above the processed film; forming a secondfilm pattern covering a portion of the first film pattern and a thirdfilm pattern connected to the second film pattern together above theprocessed film, the third film pattern having a width dimension narrowerthan the first film pattern, and to be a line pattern of a line andspace pattern; forming a fourth film conformally so as to cover aremaining portion of the first film pattern, the second film pattern,and the third film pattern; forming a film pattern by the fourth film ona side face of the first film pattern and a plurality of film patternsby the fourth film to be a line pattern of a line and space pattern onboth side faces of the third film pattern, by etching the fourth filmuntil a remaining portion surface of the first film pattern, a surfaceof the second film pattern, and a surface of the third film pattern areexposed; removing the second film pattern and the third film pattern;and etching the processed film by using the plurality of film patternsby the fourth film formed on the both side faces of the third filmpattern and a wide pattern formed by combining the first film patternand the film pattern by the fourth film formed on the side face of thefirst film pattern as masks.
 2. The method according to claim 1, whereinthe second film pattern and the third film pattern are formed of acoated organic film.
 3. The method according to claim 1, wherein asilicon oxide film (SiO₂ film) is used as the fourth film.
 4. The methodaccording to claim 1, wherein the film pattern by the fourth film havinga line width less than a resolution limit of exposure is formed on theside face of the first film pattern by etching the fourth film.
 5. Themethod according to claim 4, wherein a plurality of film patterns by thefourth film having the line width less than the resolution limit ofexposure are formed on both side faces of the second film pattern byetching the fourth film.
 6. The method according to claim 1, furthercomprising: forming a conductive film in a lower layer of the processedfilm; and etching the conductive film using a remaining processed filmas a mask after the processed film being etched.
 7. The method accordingto claim 1, wherein two first film patterns to be a pair are aligned andformed when the first pattern is formed, the second film pattern isformed by covering a portion of each of the two first film patternsrespectively, a first wide pattern combining one of the two first filmpatterns and a film pattern by the fourth film formed on a side face ofthe one of the two first film patterns and a second wide patterncombining an another one of the two first film patterns and a filmpattern by the fourth film formed on a side face of the another one ofthe two first film patterns are formed, a film pattern of the pluralityof film patterns by the fourth film formed on an one side face of thethird film pattern is connected to the first wide pattern using one ofthe two first film patterns, and a film pattern of the plurality of filmpatterns by the fourth film formed on an another side face of the thirdfilm pattern is connected to the second wide pattern using the anotherone of the two first film patterns.
 8. The method according to claim 1,wherein the plurality of film patterns by the fourth film having a linewidth less than a resolution limit of exposure are formed on the bothside faces of the third film pattern by etching the fourth film.
 9. Themethod according to claim 6, wherein the conductive film remaining afteretching using as a next mask the processed film remaining after etchingusing the film pattern by the fourth film formed on the side face of thefirst film pattern and the first film pattern as the masks, is used as ahook-up of a wire.
 10. The method according to claim 9, wherein theconductive film remaining after etching using as the next mask theprocessed film remaining after the etching using the plurality of filmpatterns by the fourth film formed on the side face of the third filmpattern as the mask, is used as a wire.
 11. The method according toclaim 10, wherein a silicon (Si) film is used as the conductive film.12. The method according to claim 1, further comprising: forming acoated organic film so as to cover the first film pattern forplanarization after the first film pattern being formed.
 13. The methodaccording to claim 12, wherein the second film pattern and the thirdfilm pattern are formed by processing the coated organic film.
 14. Amethod for forming a pattern, comprising: forming two first convexpatterns to be paired having a wide width dimension side by side in afirst region above a substrate above which a conductive film is formed,forming second convex patterns on an outer side face of each of the twofirst convex patterns respectively and also two third convex patterns,each of which connected to one of the second convex patterns on theouter side face of the two first convex patterns, to be adjacent twoline patterns of a line and space pattern in a second region above thesubstrate in a line width substantially a same width as the secondconvex patterns and narrower than a width dimension of the first convexpatterns, and etching the conductive film in ways that allow the first,second, and third convex patterns to be transferred.
 15. The methodaccording to claim 14, wherein the second and third convex patterns areformed in the line width less than a resolution limit of exposure. 16.The method according to claim 14, wherein the second region is a wiringregion and the line and space pattern of a wire is formed by etching theconductive film in ways that allow the third convex patterns to betransferred.
 17. The method according to claim 16, wherein the firstregion is a hook-up region and a hook-up is formed by etching theconductive film in ways that allow a wide pattern combining each of thefirst convex patterns and one of the second convex patterns formed onthe outer side face thereof to be transferred.
 18. The method accordingto claim 14, further comprising: forming a coated organic film so as tocover the two first convex patterns for planarization after the twofirst convex patterns being formed.
 19. The method according to claim18, further comprising: forming a film pattern by the coated organicfilm in the first region so as to extend over the two first convexpatterns.
 20. The method according to claim 19, further comprising:forming a line pattern connected to the film pattern by the coatedorganic film in the second region, the third convex patterns beingformed on both side faces of the line pattern by the coated organicfilm.